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CPAN::Forum
Verilog-Perl
This section of the site is for discussing the Verilog-Perl CPAN distribution.
All the posts related to modules of WSNYDER.
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| Title | Thread | Date | Posted by |
|---|---|---|---|
| input int; | 36 days ago | avshae | |
| A few proposed changes to Verilog::Netlist | 109 days ago | mcorazao | |
| Verilog::SigParaser does not take prepocessed output | 411 days ago | dbsingh1880 | |
| Re: How to use read_libraries to resolve the reference? | (+1) | 509 days ago | walter |
| escaped names termined with whitespace | 509 days ago | chinnery | |
| How can I get at a parameter defined in a module from the data structure ? | 523 days ago | berke | |
| How could I write out my new cell or module? | 539 days ago | walter | |
| How to use read_libraries to resolve the reference? | 706 days ago | guc | |
| How to use read_libraries to resolve the reference? | (+1) | 706 days ago | guc |
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