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Hi,
I've a parameter in a submodule which I would like to access in the data structure returned
"link" I guess it is.
1) Is there a procedure to get at the parameters ? Looks like it IS in there ("x" in debugger).
2) What is the data structure mapping for this ? (got a map of your internal data structure so I can access this ?)
For example, I want to find the value of all parameters "TD" in all modules.
Second example, I want to get and check all parameter values of parameter "TD" in xi_tgate module.
Thanx much if you can help.
Tim
VERILOG:
// Verilog HDL for "XI_MacrosLib", "xi_tgate" "functional"
// Library - XI_MacrosLib, Cell - xi_tgate
// Functional model
module xi_tgate ( A, Y, C, CB );
inout Y, A;
input C, CB;
parameter TD = 1;
nmos #TD ( Y, A, C );
pmos #TD ( Y, A, CB );
endmodule // xi_tgate
// Library - rnr_berke, Cell - mactest, View - schematic
// LAST TIME SAVED: Jun 27 10:12:29 2007
// NETLIST TIME: Jun 27 10:12:45 2007
`timescale 1ps / 1ps
module mactest ( out, in, s0, s1 );
output out;
input in, s0, s1;
specify
specparam CDS_LIBNAME = "rnr_berke";
specparam CDS_CELLNAME = "mactest";
specparam CDS_VIEWNAME = "schematic";
endspecify
not ( strong0,strong1 ) #(1) I3 ( net7, s0);
not ( strong0,strong1 ) #(1) I2 ( net5, s1);
xi_tgate I1 ( in, out, s0, net7);
xi_tgate I0 ( in, out, net5, s1);
endmodule
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