One issue that I've noticed is that escaped names, e.g. \foo[1] are terminated white whitespace when stored. e.g. This would be stored as "\foo[1] ". So when I call find_cell("\foo[1]") nothing is returned - I have to use find_cell("\foo[1] "). The Verilog standard is that an escaped name is terminated by a space, tab or newline, but that terminator shouldn't actually be part of the name. Though a terminator (i.e. space) would still need to be used in the output Verilog. Thanks, Dave.