Verilog-Perl - Verilog::SigParaser does not take prepocessed output

Posted on Thu Oct 18 14:35:26 2007 by dbsingh1880
Verilog::SigParaser does not take prepocessed output
I am trying to use the Verilog-Perl package for parsing some verilog files . But when I try and pass preprocessed output to SigParser (as described in package synopsys) object +I get error shown below. line of code causing problem is "$parser->parse_prepoc_file($pp);" Kindly let me know how to resolve this. Error Can't locate auto/Verilog/SigParser/parse_prepo.al in @INC (@INC contains: /usr/lib/perl5/5.8/cygwin /usr/lib/perl5/5.8 /usr/lib/perl5/site_perl/5.8/cygwin /usr/lib +/perl5/site_perl/5.8 /usr/lib/perl5/site_perl/5.8/cygwin /usr/lib/perl5/site_perl/5.8 /usr/lib/per +l5/vendor_perl/5.8/cygwin /usr/lib/perl5/vendor_perl/5.8 /usr/lib/perl5/vendor_perl/5.8/cygwin /us +r/lib/perl5/vendor_perl/5.8 .) at ./vp11.pl line 16
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